A Schottky diode is a unipolar device using electrons as carriers, which is characterized by high switching speed and low forward voltage drop. The limitations of Schottky diodes are the relatively low reverse voltage tolerance and the relatively high reverse leakage current. The limitations are related to the Schottky barrier determined by the metal work function of the metal electrode, the band gap of the intrinsic semiconductor, the type and concentration of dopants in the semiconductor layer, and other factors. In contrast to the Schottky diode, a P-N junction diode is a bipolar device that can pass more current than the Schottky diode. However, the P-N junction diode has a forward voltage drop higher than that of the Schottky diode, and takes longer reverse recovery time due to a slow and random recombination of electrons and holes during the recovery period.
For combining the benefits of the Schottky diode and the P-N junction diode, a configuration of a gated diode device has been disclosed. In the gated diode, the equi-potential gate and source electrodes of a planar MOSFET are served as the anode, and the drain electrode at the backside of the wafer is served as the cathode. The gated diode device has comparable or lower forward voltage drop with respect to the Schottky diode. The reverse leakage current of the gated diode device is similar to the P-N junction diode, but is lower than the Schottky diode. The reverse recovery time at high temperature of the gated diode device is similar to the Schottky diode. The interface tolerance temperature of the gated diode device is higher than the Schottky diode. In practical applications, the gated diode device is advantageous over the Schottky diode.
A typical gated diode device has been disclosed in U.S. Pat. No. 6,624,030, which is entitled “RECTIFIER DEVICE HAVING A LATERALLY GRADED P-N JUNCTION FOR A CHANNEL REGION”. Please refer to FIGS. 1A˜1I, which schematically illustrate a method of manufacturing a gated diode device.
Firstly, as shown in FIG. 1A, an N+ substrate 20 with an N− epitaxial layer 22 grown thereon is provided, wherein a field oxide layer 50 is grown on the surface of the N− epitaxial layer 22. Then, as shown in FIG. 1B, a photoresist layer 52 is formed on the field oxide layer 50. A first photolithography and etching process is performed to partially remove the field oxide layer 50. Then, a first ion-implanting process is performed to dope the substrate with a P-type dopant (e.g. boron) through openings in the photoresist layer 52. Then, a boron thermal drive-in process is perform to form edge P-doped structures 28 and a center P-doped structure 30 (FIG. 10). Then, a second ion-implanting process is performed to dope the substrate with BF2. Then, a second photolithography and etching process is performed to use a photoresist layer 54 to cover the periphery of the device region and remove the field oxide layer 50 in the center of the device region (FIG. 1D and FIG. 1E). As shown in FIG. 1F, a gate silicon oxide layer 56, a polysilicon layer 58 and a silicon nitride layer 60 are sequentially grown, and an arsenic implantation process is made. Then, as shown in FIG. 1G, an oxide layer 62 is formed by chemical vapor deposition. Then, a third photolithography and etching process is performed to form a gate-pattern photoresist layer 64 over the oxide layer 62. Then, a wet etching process is performed to etch the oxide layer 62 while leaving the oxide layer 62 under the gate-pattern photoresist layer 64 (FIG. 1H). Then, a dry etching process is performed to partially remove the silicon nitride layer 60, and a third ion-implanting process is performed to dope the substrate with boron ion (FIG. 1I). Then, the remaining photoresist layer 64 is removed, and a fourth ion-implanting process is performed to dope the substrate with boron ion to form a P-type pocket 36 (FIG. 1J). Then, a wet etching process is performed to remove the silicon oxide layer 62, and a dry etching process is performed to partially remove the polysilicon layer 58 (FIG. 1K). Then, an arsenic implantation process is made to form an N-doped source/drain region 24, a wet etching process is performed to remove the silicon nitride layer 60, and an arsenic implantation process is made (FIG. 1L). Meanwhile, some fabricating steps of the gated diode device have been done. After subsequent steps (e.g. metallic layer formation, photolithography and etching process, and so on) are carried out, the front-end process is completed.
In comparison with the Schottky diode, the gated diode device fabricated by the above method has comparable forward voltage drop, lower reverse leakage current, higher interface tolerance temperature, better reliability result and longer reverse recovery time (at the room temperature).